DVConUS 2023 Verification Horizons is Out
Some of you may have wondered for the past few years why we chose to use the name Verification Horizons for both our blog and our newsletter. The first reason is that it’s a pretty cool name (if I do say so myself). We actually started the newsletter way back in 2005 while the blog didn’t start until a few years later. But now, they’re pretty much one and the same.
We are now publishing our Verification Horizons newsletter articles on the Verification Academy website instead of as a PDF document. You’ll still be able to print the html versions if you prefer that approach, but the feedback we’ve gotten over the years is that most of our audience prefers to read things online, so that’s what we’re doing. In this blog post, I’ll be doing my traditional Editor’s Introduction to, in this case, our DVConUS 2023 edition of the Verification Horizons newsletter. I’m sure you’ll find the articles interesting and helpful.
In our first article, “Everything, Everywhere, All at Once: Big Data Reimagines Verification Predictability and Efficiency,” my colleague Darron May explains how predictive analytics can be used to apply a Big Data approach to help manage your verification process. We’re very excited to introduce our Questa™ Verification IQ data-driven verification solution that will help you explore the different relationships between the vast amounts of data that we all are (or should be) collecting throughout our verification processes. This article provides some great background on just how Verification IQ does what it does.
Our next article, “Democratizing digital-centric mixed-signal verification methodologies,” by Sumit Vishwakarma, gives us a great overview of the ways in which analog and mixed-signal can take advantage of some of the methodologies that we’ve employed in digital verification for many years.
Our third article from our Siemens family is “Lane Margining at Receiver and its Application Through a Pipe Message Bus,” by Sachin Mishra. This article gives an in-depth look at the new lane margining feature of PCIe gen4, and how designers can use it to create more robust systems.
We begin our Partners’ Corner section with two great articles on different aspects of RISC-V verification. First we have “The RISC-V Verification Interface (RVVI) – Test Infrastructure and Methodology Guidelines,” from our friends at Imperas Software. As we all know, when you introduce flexibility into a design, it becomes more difficult to verify. This can be particularly true when it comes to RISC-V designs, since everyone can design their own processor extensions and it falls to the verification team to make sure that they work. This article provides an overview of the RVVI and explains how it can improve the quality and resusability of your processor verification efforts. If you’re using RISC-V in your project, or thinking of using it, I encourage you to check out this article.
In addition, we also have “A Formal-Based Approach for Efficient RISC-V Processor Verification” from our friends at Codasip. As we know, there are certain bugs that are just easier to find via formal verification than simulation, and it is quite easy to introduce such bugs when you add advanced features to your custom RISC-V processor. In this article, they provide a case study of how they used the Siemens EDA Processor Verification App to verify their L31 RISC-V core. Whether you are using the Processor Verification App or not, you’ll learn a few things that ought to help you on your next RISC-V project. And if you’re thinking of using the L31, you’ll be confident that it’s been properly verified.
We continue in the formal vein with “Jumpstart Your Formal Verification with a Little Help,” from our friends at Doulos. I’ve known Doug Smith for many years, and I was not surprised when he submitted such a comprehensive article. In this article, Doug walks us through how to utilize “helper code” to not only simplify some important assertions, but also to be able to apply assertions to problems that we otherwise would not have been able to verify formally.
Last but not least, our friends at Silicon Interfaces bring us “Resolving Metastability Issues for Multi-Clock SOC Environments for I2C.” In this article, they present a case study of how they used the Questa Clock Domain Crossing (CDC) verification tool to solve metastability issues that arose between parts of the design with different clocks. This is a problem that many of us face in our projects, and I’m sure you’ll find some interesting nuggets to apply to your own multi-clock-domain designs.
If you’re reading this before or during DVConUS, I hope you can stop by the Siemens booth on the exhibit floor and say hi. Or look for me around the conference. I always love hearing from colleagues who have enjoyed and benefitted from the many resources we provide, whether it’s blog posts, newletter articles, or other valuable content on Verification Academy.
Respectfully submitted,
Tom Fitzpatrick
Editor, Verification Horizons
