Let’s meet in Munich at DVCon Europe 2023

DVCon Europe celebrates its 10th anniversary this year!  What started as a small conference to complement DVCon in the United States, has grown into a full-fledged conference on electronic system design and verification issues that brings practicing designer and verification engineers together with academic researchers.  DVCon Europe will be held 14-15 November 2023 in Munich Germany with the SystemC Evolution Day to be held the following day on 16 November 2023.  If you have not already registered for the event, click here to register.  Siemens will also host a post conference user event, osmosis, for the formal verification community on 16 November 2023 which is discussed in a blog post here.

Siemens is a Gold Sponsor and has a wide variety of new and improved flows to share with you from low power design and verification of AI/ML accelerators and RISC-V processors, designer focused solutions, and more.  Here are details on our sponsored tutorial, participation in the Accellera tutorial on advances of its CDC standardization effort, and an AI-centric panel session:

• Tutorial 3.2: Tuesday, November 14, 11:45 am – 1:15 pm
  Model-Based Approach for Developing Optimal HW/SW Architectures for AI Systems
  Petri Solanti and Russell Klein, Siemens EDA
  
  Artificial Intelligence (AI) algorithms in a real-time operating environment require huge amounts of computation resources and process gigabytes of data. An efficient AI system needs carefully analyzed Hardware/Software partitioning and architecture that can meet real-time processing, energy efficiency, and cost requirements. Using a Model-Based Cybertronic Systems Engineering (MBCSE) methodology the design complexity and challenging requirements can be tackled.
  
  This tutorial will demonstrate the design process as a transformation of an AI algorithm from a Python program to an efficient, low power implementation with a mix of hardware and software elements. The design process applies Architecture Analysis & Design Integrated Approach (Arcadia), SystemC-based HW/SW co-architecting and High-Level Synthesis (HLS) methodologies.
  
  
• Tutorial 3.3: Tuesday, November 14, 2:15 pm – 3:45 pm
  Making the impossible possible: CDC and RDC closure with abstracts from different tools
  Diana Kalel, STMicro
  Jean-Christophe Bringnone, STMicro
  Abdel Ayari (for Farhad Ahmed), Siemens
  Eldad Falik, Intel
  Jerome Avezou, Synopsys
  Bill Gascoyne, Blue Pearl Software
  Kranthi Pamarthi, Renesas
  
  This tutorial has two main sections: The first section is a simple presentation about the basic concepts and definitions of CDC-RDC design and verification. The second section is a demo to show the different steps of the CDC verification flow.
  
  A small and illustrative RTL test case with at least two EDA verification tools will be used to raise awareness about the importance of a new standard that makes the CDC models portable and reusable between the different EDA tools.
  
  
• Panel: Wednesday, November 15, 9:15 am – 10:15 am
  “All AI, All the Time” Poses New Challenges for Traditional Verification
  Moderator – Paul Dempsey, Editor in Chief, Tech Design Forum
  Panelists
  Jean-Marie Brunet, VP & GM, Hardware-Assisted Verification, Siemens
  Micheala Blott, Senior Fellow, AMD
  Daniel Schostak, Arm Architect and Fellow – Verification, Arm
  Anil Deshpande, Director of Engineering, Samsung Semiconductor India
  Lu Dai, Accellera Chair – Senior Director of Engineering, Qualcomm
  
  AI, including generative AI platforms such as ChatGPT, are straining data centers, hyperscalers and cloud computing, all the while optimizing and accelerating processes and creating new challenges for traditional verification technologies.
  Verification tools have had some form of in-built intelligence for many years that would not be highlighted in any datasheet or whitepaper. Verification tool providers are now attempting to offer AI and machine learning capabilities within their functional verification solutions to improve performance and productivity, though questions remain on whether results are impressive enough to meet assumptions about current and future capabilities.
  
  The panel of verification experts and vendors will discuss how best to utilize AI/ML for functional verification and consider whether AI/ML-based verification tools will be able to keep up with the growing AI architecture design needs.
  
  Attendees should be prepared for a discussion that addresses how the verification community will manage the emerging world of “All AI, All the Time.”