Ready for a Verification Extravaganza in the Land of Verification Engineers?

I have always been wanting to contribute to the growing verification engineering community in India, which Mentor’s CEO Wally Rhines calls “the largest verification market in the world”. So when I first accompanied the affable Dennis Brophy to the IEEE India office back in April of 2014 to discuss the possibility of having a DVCon in India, I knew I was at the right place at the right time and it was opportunity to contribute to this community.

I has been two years since that meeting, I don’t have to write about how big a success the first ever DVCon India in 2014 was. I’m glad I played a small part by being on the Technical Program Committee on the DV track, reviewing various abstracts. It is a responsibility which I thoroughly enjoyed. This year in addition to being on the TPC, I am contributing as the Chair for Tutorials and Posters. I am eagerly looking forward to the second edition of the Verification Extravaganza which is on 10^th and 11^th Sept 2015 and the amazing agenda we have planned for attendees.

Day 1 of the conference is dedicated to keynotes, panel discussions and tutorials while day 2 is dedicated fully to Papers with a DV track and a panel in addition to papers in a ESL track. Participants are free to attend any track and can move between tracks. This year we had many sponsored tutorials submissions hence, there will be three parallel tutorial tracks, one on the DV side and two on the ESL track.

Below please find a list of those that Mentor Graphics will be presenting at:

• Keynote from Harry Foster discussing the growing complexity across the entire design ecosystem
  Thursday, September 10, 2015
  9:45am – 10:30am
  Grand Ball Room, The Leela Palace
  More Information >
  Register for this event >

• Creating SystemVerilog UVM Testbenches for Simulation and Emulation Platform Portability to Boost Block-to-System Verification Productivity
  Thursday, September 10, 2015
  1:30pm – 3:00pm
  DV Track, Diya, The Leela Palace
  More Information >
  Register for this event >

• Leveraging Portable Stimulus across Domains and Disciplines
  Thursday, September 10, 2015
  1:30pm – 3:00pm
  ESL Track, Royal Ball Room, The Leela Palace
  More Information >
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• Expediting the code coverage closure using Static Formal Techniques – A proven approach at block and SoC Levels!
  Thursday, September 10, 2015
  1:30pm – 3:00pm
  DV Track, Grand Ball Room, The Leela Palace
  More Information >
  Register for this event >

• FPGA Implementation Validation and Debug Tutorial
  Thursday, September 10, 2015
  1:30pm – 3:00pm
  DV Track, Sitara, The Leela Palace
  More Information >
  Register for this event >

The papers on day 2 are primarily split into 3 parallel tracks, one on DV track and 2 parallel tracks on ESL. Within the DV track, one area is dedicated to UVM/SV. The other categories within the DV track will cover Portable Stimulus & Graph Based Stimulus, AMS, SoC & Stimulus Generation, Emulation, Acceleration and Prototyping & a generic selected category. The surprise among the categories is Portable Stimulus, which was a tutorial in last year however has continued to be of high interest and sessions will build on last year’s initial tutorial.

Overall there is an exciting mix of keynotes, tutorials, panels, papers and posters, which will make two exceptional days of learning, networking and fun. I look forward to seeing at DVCon India, 2015 and if you see me at the show, please come say hello and let me know what you think of the conference.