Part 2: The 2016 Wilson Research Group Functional Verification Study

FPGA Verification Effort Trends

This blog is a continuation of a series of blogs related to the 2016 Wilson Research Group Functional Verification Study (click here). In my previous blog (click here), I focused on FPGA design trends. In this blog, I am updating my original 2014 blog with the findings from our new study related to the effort spent in verification.

Directly asking study participants how much effort they spend in verification will not work. The reason is that it’s hard to find a paper or article on verification that doesn’t start with the phrase: “Seventy percent of a project’s effort is spent in verification…” In other words, the industry is already biased to respond with this effort value. Yet, there are really no creditable references to quantify this value.

I don’t believe that there is a simple answer to the question, “How much effort was spent on verification in your last project?” In fact, I believe that it is necessary to look at multiple data points derived from multiple questions to truly get a sense of effort spent in verification. And that’s what we did in our functional verification study.

Total FPGA Project Time Spent in Verification

To try to assess the effort spent in verification, let’s begin by looking at one data point, which is the total project time spent in verification. Figure 1 shows the trends in total percentage of FPGA project time spent in verification by comparing the 2012 Wilson Research Group study (in violet), and the 2014 Wilson Research Group study (in light pink), and the 2016 Wilson Research Group study (in red).

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Figure 1. Percentage of FPGA project time spent in verification

Between the years 2012 and 2016 we see a 2.79 percent compounded annual growth rate (CAGR) increase in the average time an FPGA project spends in verification. Historically, FPGA projects have spent less time in verification than ASIC/IC projects. The FPGA project strategy has traditionally been to get to the lab as soon as possible, and then iterate on issues in the lab. In a future blog I’ll show data that indicates this strategy does not necessarily yield good results in terms of meeting project schedule or quality objectives. Also, this lab-focused approach to FPGA verification becomes less effective as FPGA complexity increases.

Peak Number of Design and Verification Engineers

Perhaps one of the biggest challenges in design and verification today is identifying solutions to increase productivity and control engineering headcount. Figure 2 shows the mean peak number of design and verification engineers working on an FPGA project. Again, this is an industry average since some projects have many engineers while other projects have few.

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Figure 2. Mean peak number of engineers working on an FPGA project

You can see that the compounded annual growth rate (CAGR) for the peak number of FPGA design engineers between 2012 and 2014 increased by 4.9 percent, while the CAGR for the peak number of FPGA verification engineers increased by 20.9 percent. This demand for verification engineers on FPGA projects is one indicator of growing verification complexity in FPGA designs. However, the increasing demand for verification engineers slowed in 2016. Also note that the ratio of design engineers versus verification engineers is approaching 1-to-1, which is a similar trend that happened on traditional ASIC/IC designs back in 2012.

In my next blog (click here) I focus on the time that FPGA design and verification engineers spend in various task.

Quick links to the 2016 Wilson Research Group Study results

FPGA Verification Effort Trends

Total FPGA Project Time Spent in Verification

Peak Number of Design and Verification Engineers

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