Thought Leadership

A New Twist at DVConUS

This year at DVCon US, Mentor is going to add some sizzle to our booth (#1005) during the exhibit hours. In addition to our stellar demo staff who are always available to answer questions and show you the latest capabilities of our tools, we’re also going to be hosting a number of technical presentations in our new Verification Theater. I’ll be kicking things off on Monday at 5:00 on the exhibit floor with “Portable Stimulus from IP to SoC – Achieve More Verification with Questa inFact,” where I’ll share with you some practical tips on how to use the new Portable Test and Stimulus Standard to both improve the quality of your verification and to reuse stimulus and coverage goals as you move from the IP-level to full SoC verification. I hope you’ll come and join me for this informative session.

Additional sessions will include:

  • Monday, Feb 25
    • 5:45 – Accelerate SoC Power, Veloce Strato – PowerPro [Shantanu Samant]
    • 6:30 – Exploring Veloce DFT and Fault Apps [Robert Serphillips]
  • Tuesday, Feb 26
    • 3:00 – Mentor Safe IC – ISO 26262 & IEC 61508 Functional Safety [Jacob Wiltgen]
    • 3:45 – Adding Determinism to Power in Early RTL Using Metrics [Jay Nataranjan]
    • 4:30 – Scaling Acceleration Productivity Beyond Hardware [Steve Bailey]
    • 5:15 – Adding Determinism to Power in Early RTL Using Metrics [Jay Nataranjan]
  • Wednesday, Feb 27
    • 3:00 – Verification Signoff of HLS C++/SystemC Designs [Dave Aerne]
    • 4:00 – An Emulation Strategy for AI and ML Designs [Vijay Chobisa]
    • 5:00 – Advanced UVM Debugging [Moses Satyasakaran]

So if you’re at DVCon with an exhibit-only (i.e. “free”) badge, want to take a break from one of the afternoon sessions for a bit, or are just looking for some more information about some great verification technology, please come and join us in our Verification Theater at booth #1005.

For those of you with access to the paper sessions on Wednesday, please join my colleague Matthew Ballance (our Portable Stimulus guru) and myself as we each present a paper in the “Applications of the New Portable Stimulus Standard” session at 10am on Wednesday.

I look forward to seeing you at the conference.

Tom Fitzpatrick

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This article first appeared on the Siemens Digital Industries Software blog at https://blogs.stage.sw.siemens.com/verificationhorizons/2019/02/14/a-new-twist-at-dvconus/