Chris Spear

Chris brings over forty years of EDA expertise to Siemens customers. Holding a degree in electrical engineering from Cornell University, Chris has developed deep roots in the EDA industry, including as a Principal Application Consultant. Chris is also an industry author, writing the 2012 best-selling “SystemVerilog for Verification” and developing the IEEE standard for random seeding and File I/O PLI package that is part of SystemVerilog. Having taught thousands of engineers around the world, Chris is driven by a passion for learning new techniques and then helping others learn best practices for hardware verification. Outside of work, you may see Chris bicycling over 12,000-foot mountain passes.

Starting Your UVM Simulation

Starting Your UVM Simulation

October 10, 2023

Introduction What happens when you start your simulation with a UVM test bench? Where should you put the uvm_config_db::set() calls…

By Chris Spear
3 MIN READ

A Hitchhiker’s Guide to DVCon US ’23

June 27, 2023

Where can you improve your verification skills? In March 2023 I attended DVCon US, the Verification and Design Conference in…

By Chris Spear
3 MIN READ
Pool of parameterized handles in SystemVerilog

Groups of Class Specializations in SystemVerilog

April 25, 2023

Introduction In a previous post, I said that in SystemVerilog, once you specialize a class, you can not make a…

By Chris Spear
3 MIN READ
The UVM string-based Factory can print base and derived objects

The UVM Factory Revealed, Part 2

January 25, 2023

Introduction This is a follow up to last week’s high-level post on the UVM Factory. Now let’s get technical! Here…

By Chris Spear
3 MIN READ
The UVM type-based Factory can print base and derived objects

UVM Factory Revealed, Part 1

January 20, 2023

Introduction When you first learn UVM, most of the concepts make sense, even if you are new to Object-Oriented Programming….

By Chris Spear
4 MIN READ
Three ice cream cones, vanilla, chocolate, and strawberry

Does Your UVM Flavor Have Sprinkles?

October 20, 2022

Introduction UVM is a standard, so that means that every company writes their testbenches the same, universally interchangeable, right? Not…

By Chris Spear
4 MIN READ
A pool of specialized classes

Dig a Pool of Specialized SystemVerilog Classes

October 17, 2022

Introduction SystemVerilog classes are a great way to encapsulate both variables and the routines that operates on them. What if…

By Chris Spear
4 MIN READ
Implicit handle: this

SystemVerilog: Implicit handles

September 6, 2022

Introduction In the last blog post [SC(SECL1] Farmer Ted asked you to keep track of his animals and you wrote some…

By Chris Spear
4 MIN READ
SystemVerilog: Class Member Visibility

SystemVerilog: Class Member Visibility

August 29, 2022

Introduction Farmer Ted wants to keep track of the animals on his property and asks you to write the code….

By Chris Spear
3 MIN READ