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Dave Rich

Dave Rich is Verification Technologist at Mentor Graphics and is one of the authors of Mentor’s Advanced Verification Methodology cookbook. He began his career as a design and verification engineer in 1981 at Data General. In 1987, he joined Gateway Design Automation as one of the first application engineers to support Verilog-XL. At Gateway, he helped design many of the early features of the Verilog Hardware Description Language (HDL), and after Cadence acquired Gateway, helped prepare the Language Reference Manual (LRM) that would eventually be donated to the newly formed Open Verilog International. In 1995, he joined another Verilog simulation company, Frontline Design Automation as an AE manager and later as a Product Manager after it was acquired by Avant!. In 1998, he joined Ambit Design and worked as a consulting engineer for both synthesis and simulation products after it was acquired by Cadence. In 2000, he joined Co-Design Automation as Director of Application Engineering where the Superlog HDL was being developed that eventually became the basis of the Accellera SystemVerilog 3.0 standard. Co-Design Automation was acquired by Synopsys in 2002. Dave began work on numerous technical committees within Accellera and later the IEEE P1800 working group, which he continues today.

The Art of Deprecation

The Art of Deprecation

March 23, 2010

At a recent SystemVerilog requirements gathering meeting,I was quite amused to see “deprecating features” come out as one of the…

By Dave Rich
3 MIN READ
SystemVerilog: A time for change? Maybe not.

SystemVerilog: A time for change? Maybe not.

February 25, 2010

The SystemVerilog IEEE 1800-2009 Language Reference Manual (LRM) was published a few months ago with an unprecedented 472 updates. That’s…

By Dave Rich
2 MIN READ
SystemVerilog: The finer details of $unit versus $root.

SystemVerilog: The finer details of $unit versus $root.

September 25, 2009

Another installment of “Longwinded Answers to Frequent SystemVerilog Questions: $root versus $unit” Believe me – I tried to make this…

By Dave Rich
3 MIN READ
SystemVerilog Coding Guidelines

SystemVerilog Coding Guidelines

September 11, 2009

I have lots of blog entries about 95% ready to publish. This entry is from an e-mail I wrote a…

By Dave Rich
2 MIN READ
The Language versus The Methodology

The Language versus The Methodology

July 7, 2009

I’ve been around simulation and synthesis languages for a while; back when you needed an NDA to see the Verilog…

By Dave Rich
3 MIN READ
Are Program Blocks Necessary?

Are Program Blocks Necessary?

May 7, 2009

That’s a frequent SystemVerilog question I’m asked. Program blocks came directly from donation of the Vera language to SystemVerilog by…

By Dave Rich
3 MIN READ

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