SystemVerilog Race Condition Challenge

If there’s one thing I’ve learned since coming to Mentor early last year, it’s that the SystemVerilog language gives developers…

Methodology by Example – 6 Approaches to Verification

Methodology by Example – 6 Approaches to Verification

This blog is an exciting next step – exciting for me at least! – that builds on what I proposed…

The Ideal Verification Timeline

The Ideal Verification Timeline

Our discussion around building integrated verification methodologies started with where techniques apply to design by plotting options for verifying low,…

Tools In A Methodology Toolbox

Tools In A Methodology Toolbox

To understand how techniques fit together as part of a comprehensive verification methodology, we’re mapping techniques as a function of…

Verification Methodology Reset

Verification Methodology Reset

Discussion around verification methodologies have been going on for a couple decades. It started back around 2000 with the emergence…

Building Integrated Verification Flows – Round 2

Building Integrated Verification Flows – Round 2

Verification methodology has been a continuous discussion in our industry for a good 20 years now. I’ve dabbled in that…

Questa VRM is the New MS Project

Questa VRM is the New MS Project

I’ve written extensively about agile development from the point of a verification engineer. From the beginning, I’ve been firmly of…

The Beginning Of The End For Coverage

The Beginning Of The End For Coverage

Before we get started here, I’ll assure you it’s not as it sounds. I’m not talking about the end of…

New Job Excitement

New Job Excitement

This is my first Verification Horizons blog since joining the Mentor Product Engineering team in January. I’m excited to be…