Well, another DAC is behind us, and you know what that means. That’s right, the super-sized DAC issue of Verification…
When we looked at requirements for UVM in Accellera, one of the highest priority requests from users was to have…
By now you’ve probably heard that Accellera approved the Universal Verification Methodology Standard (UVM1.0) today. This announcement is the culmination…
Hi Everyone, Just wanted to let you know that the latest edition of our Verification Horizons newsletter is available here….
Technorati Tags: UVM,SystemVerilog,RAL,OVM The development of UVM in the Accellera VIP-TSC brings up, yet again, the age-old philosophical question: should…
In the classic Sherlock Holmes story, “Silver Blaze,” Holmes realizes that the family dog didn’t bark when the suspect entered…
Last year, the Accellera VIP-TSC spent quite a lot of time (I know, because I was there) defining a standard…
For those of you who didn’t make it to DVCon this year, you missed one of the things that makes…
I see that Synopsys has finally released VMM1.2. Congratulations, guys. There will be plenty of opportunity over the coming weeks…
