Decoding LLM Hallucinations: Insights and Taming them for EDA Applications

What are Large Language Model’s hallucinations. LLMs will be powerful EDA productivity tool once we know what caused it and how to deal with their adverse effects.

Siemens EDA at the 60th DAC

Please mark your calendars for the highly anticipated 60th anniversary Design Automation Conference (DAC). The 60th DAC will take place…

UVM Debug? Just nature doing what it does

Bent Tools and other Horrors From the Garden and UVM Debug – or Are You Still Debugging with $display?

I can’t take credit for the great flowers in the garden. It’s the tremendous rain we’ve had in California this…

Pool of parameterized handles in SystemVerilog

Groups of Class Specializations in SystemVerilog

Introduction In a previous post, I said that in SystemVerilog, once you specialize a class, you can not make a…

DVConUS 2023 Verification Horizons is Out

Some of you may have wondered for the past few years why we chose to use the name Verification Horizons…

ML for Verification

Big Data for Verification – Inspiration from Large Language Models

The importance of verification data learned from training Large Language Models. In DVCon will share an overview of ML applications in verification and . present VIQ tutorial on how data can empower verification, with demos of existing ML applications.

3 Ways DVCon US 2023 is Going to be Different This Year

1 – The Tuesday keynote For the first F2F/IRL DVCon since 2020, the Steering Committee wanted a fresh alternative to…

DVCon U.S. 2023: Expanded Accellera content

DVCon U.S. 2023 will be full of opportunities to learn about advances in design and verification technology as it returns…

To UVM Config or Not at DVCON US – Can chatGPT do it better?

It’s all about speed and productivity for Verification Engineers and Designers. And of course, the UVM is the ticket, and…