UVM™ at DVCon 2012

UVM™ at DVCon 2012

“Ready, Set, Deploy” The last half year has seen a theme from Accellera Systems Initiative that declares its Universal Verification…

SystemC 2011 Standard Published

SystemC 2011 Standard Published

IEEE Std. 1666™-2011 Available as Free Download In November 2011 I blogged the IEEE Standards Association (SA) approved a revision…

Verification solutions that help reduce bug cost

Verification solutions that help reduce bug cost

I think very few engineers would argue with the claim that the longer a bug goes undetected, the more expensive…

Instant Replay for Debugging SoC Level Simulations

Instant Replay for Debugging SoC Level Simulations

Instant Replay Offers Multiple Views at Any Speed If you’ve watched any professional sporting event on television lately, you’ve seen…

2011 IEEE Design Automation Standards Awards

2011 IEEE Design Automation Standards Awards

The DASC Participates in IEEE Standards Association Gala Event The IEEE Computer Society Design Automation Standards Committee (DASC) participated in…

Getting started with the UVM – Using the Register Modeling package

Getting started with the UVM – Using the Register Modeling package

Adopting SystemVerilog can be challenging to some, and learning the UVM at the same time might seem overwhelming. There is…

TLM Becomes an IEEE Standard

TLM Becomes an IEEE Standard

IEEE Announces Revision to IEEE 1666™ – Adds Transaction-Level Modeling Support A significant step forward to address standards for advanced…

Worlds Standards Day 2011

Worlds Standards Day 2011

Creating Confidence Globally Today, 14 October 2011, is the day the world celebrates standards.  The leadership of the IEC, ISO…

VHS or Betamax?

VHS or Betamax?

Legacy’s Luster Lost As a follow-on to my last blog, where I shared information about Harry Foster speaking live about…