How to write a UVM transaction class? There has been a split in UVM – how to create a sequence…
What is a UVM transaction? A transaction in UVM is a class with properties for the signals, such as address…
In my last webinar I explained what happens when you import a package in SystemVerilog. There were still many questions,…
As I noted at the beginning of this series, the term “logic equivalence checking” (LEC) applies to a number of…
Introduction In my last post (Colliding Worlds of Safety Analysis), I highlighted the challenges facing safety teams and the opportunity…
After my last webinar on SystemVerilog arrays, I received several questions on the differences between arrays and structures, plus how…
You asked and I listened Thank you everyone who registered and attended my webinar on SystemVerilog arrays. There were many…
SystemVerilog has many ways to store your data. Vectors, arrays, structures, classes, and probably several more ways that I don’t…
[Preface / reminders: Part 1 of this series focused on synthesis validation with LEC and SLEC, Part 2 describes how…
