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FPGA Verification Maturity: A Quantitative Analysis

FPGA Verification Maturity: A Quantitative Analysis

In early February, I had the honor of keynoting the FPGA-forum held in the beautiful city of Trondheim, Norway. This…

Building Integrated Verification Flows – Round 2

Building Integrated Verification Flows – Round 2

Verification methodology has been a continuous discussion in our industry for a good 20 years now. I’ve dabbled in that…

The Many Flavors of Equivalence Checking: Part 3, How SLEC Brings Automated, Exhaustive Formal Analysis to Low Power Clock Gating Verification

[Preface / reminders: Part 1 of this series focused on synthesis validation with LEC and SLEC, and Part 2 describes…

DVConUS Edition of Verification Horizons is Out!

DVConUS Edition of Verification Horizons is Out!

Hi Everyone, Hello from those of us willing to brave the Coronavirus to be here at DVConUS. I am pleased…

DVCon U.S. 2020

DVCon U.S. 2020

If you have not yet registered for DVCon U.S. 2020, you can do so here. If you have the time,…

AI/ML at DVCon: From Theory to Application

AI/ML at DVCon: From Theory to Application

For many years computer systems have augmented CPUs with special purpose accelerators that are targeted at specialized tasks. Examples of…

Verification Horizons | December 2019

December 2019 Verification Horizons Newsletter is Out!

We’re happy to give you a special Christmas (or whatever gift-giving holiday you may celebrate this time of year) present:…

FMCAD 2019: The Most Important Formal Verification Conference You’ve Never Heard Of

FMCAD 2019: The Most Important Formal Verification Conference You’ve Never Heard Of

[Preface: I briefly interrupt my series on The Many Flavors of Equivalence Checking to share this report on an important…

Automotive IC Design Workshop

Automotive IC Design Workshop

Join us Thursday, November 21, 2019 at our offices in Fremont, CA for the Mentor and TowerJazz Automotive Workshop. Register…