A colleague recently asked me: Has anything changed? Do design teams tape-out nowadays without GLS (Gate-Level Simulation)? And if so,…
It’s my favorite time of year again—DVCon! And I believe that the DVCon 2015 technical program committee has put together…
It’s amazing how quickly a year goes by. DVCon 2014 seems like it was just a few months ago, and…
Accellera Approves Creation of Portable Stimulus Working Group At DVCon 2014, Mentor Graphics proposed Accellera launch an exploratory exercise, called…
FPGA Design Trends In my previous blog, I introduced the 2014 Wilson Research Group Functional Verification Study (click here). The objective…
This blog is a continuation of a series of blogs that present the highlights from the 2014 Wilson Research Group…
This is the first in a series of blogs that presents the findings from our new 2014 Wilson Research Group…
“Who Knew?” about verification IP (VIP), was the theme of a recent DeepChip post by John Cooley on December 18. …
2014 was an exciting year for formal verification to say the least, and below I call out a sampling of…
