We are truly living in the age of SoC design, where 78 percent of all designs today contain one or…
It’s hard for me to believe that SystemVerilog 3.1 was released just over 10 years ago. The 3.1 version added…
Schedules, respins, and bug classification This blog is a continuation of a series of blogs that present the highlights from…
Verification Techniques & Technologies Adoption Trends (Continued) This blog is a continuation of a series of blogs that present the…
Verification Techniques & Technologies Adoption Trends This blog is a continuation of a series of blogs that present the highlights…
Language and Library Trends (Continued) This blog is a continuation of a series of blogs that present the highlights from…
Language and Library Trends This blog is a continuation of a series of blogs that present the highlights from the…
Testbench Characteristics and Simulation Strategies This blog is a continuation of a series of blogs that present the highlights from…
You don’t need a graphic like the one below to know that multi-core SoC designs are here to stay. This one…
