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Synthesizing Hardware Assertions and Post-Silicon Debug

Synthesizing Hardware Assertions and Post-Silicon Debug

At the 2012 Design Automation Conference, I had the pleasure of moderating a panel at a workshop titled “Post-Silicon Debug:…

Virtual Emulation for Debugging

Virtual Emulation for Debugging

A system-level verification engineer once told me that his company consumes over 50% of its emulation capacity debugging failures. According…

Verification Academy: Up Close & Personal

Verification Academy: Up Close & Personal

Live & In-Person at DAC 2012! Verification Academy, the brain child of Harry Foster, Chief Verification Scientist at Mentor Graphics,…

SystemC Standardization Cycle Completes

SystemC Standardization Cycle Completes

Open-Source Proof-of-Concept Library Released Accellera Systems Initiative has released for general industry use an open-source proof-of-concept library as a companion…

Verification Standards Take Another Step Forward

Verification Standards Take Another Step Forward

Accellera Ushers in Unified Coverage Interoperability Standard (UCIS) For the past few months, Accellera’s Unified Coverage Interoperability Standards working group…

New UVM Recipe of the Month: Scoreboarding in UVM

New UVM Recipe of the Month: Scoreboarding in UVM

Hi Everyone, Just wanted to make sure you’re aware of our next Recipe of the Month online Web Seminar: Scoreboards…

Intelligent Testbench Automation – Catching on Fast

Intelligent Testbench Automation – Catching on Fast

Graph-Based Intelligent Testbench Automation While intelligent testbench automation is still reasonably new when measured in EDA years, this graph-based verification…

Two Articles You Need to Check Out

Two Articles You Need to Check Out

As Editor of Verification Horizons, I’d like to point out a couple of articles that you really need to check…

Off to DAC!

Off to DAC!

Where might our paths cross? It is always challenge to fit all the needed visits in during the Design Automation…