UVM Debug? Just nature doing what it does

Bent Tools and other Horrors From the Garden and UVM Debug – or Are You Still Debugging with $display?

I can’t take credit for the great flowers in the garden. It’s the tremendous rain we’ve had in California this…

Pool of parameterized handles in SystemVerilog

Groups of Class Specializations in SystemVerilog

Introduction In a previous post, I said that in SystemVerilog, once you specialize a class, you can not make a…

DVCon U.S. 2023: Expanded Accellera content

DVCon U.S. 2023 will be full of opportunities to learn about advances in design and verification technology as it returns…

To UVM Config or Not at DVCON US – Can chatGPT do it better?

It’s all about speed and productivity for Verification Engineers and Designers. And of course, the UVM is the ticket, and…

Re-imagining requirements management for safety-critical projects

Project teams face a host of challenges when developing semiconductors compliant to a safety critical market. Whether that’s ISO 26262…

Epilogue: The 2022 Wilson Research Group Functional Verification Study

This is the last in a sequence of blogs that presents the findings from our new 2022 Wilson Research Group…

Conclusion: The 2022 Wilson Research Group Functional Verification Study

Deeper Dive into Non-Trivial Bug Escapes This blog is a continuation of a series of blogs related to the 2022 Wilson…

Part 12: The 2022 Wilson Research Group Functional Verification Study

This blog is a continuation of a series of blogs related to the 2022 Wilson Research Group Functional Verification Study. In…

Part 11: The 2022 Wilson Research Group Functional Verification Study

This blog is a continuation of a series of blogs related to the 2022 Wilson Research Group Functional Verification Study. In my previous…