Why Is My Coverage The Way It Is?

Coverage is as Coverage does Writing coverage is an art. At least it is a skill which takes imagination, practice…

First day of school 2021 - 2022

Learn Formal the Easy Way

The sight of kids going back to school can prompt feelings of joy and renewal – or trigger less pleasant…

SPICE Turns 50!

50 years ago on 4 August 1971, the IEEE Journal of Solid-State Circuits published the Dr. Nagel and Dr. Rohrer…

Deploying Formal in a DO-254 Program

The primary focus of DO-254, referred to as ED-80 in Europe, is hardware reliability of airborne electronic hardware. DO-254 is…

SystemVerilog Class Variables and Objects

Introduction How can you visualize the relationship between classes and objects in SystemVerilog? This is the first post in a…

Explanation of “Verification” in a DO-254 program

Often times, I’m asked to define what verification activities are required for a DO-254 program. For those experienced in a…

Orchestrating an ISO26262 Fault Campaign

ISO26262 remains the state-of-the-art standard governing the activities required to prove electronics and electronic systems are safe for deployment in…

Formal Verification Experiences: Spiral Refinement Methodology for Silicon Bug Hunting

DVCon U.S. 2021 Best Paper Report – Formal Verification Experiences: Spiral Refinement Methodology for Silicon Bug Hunt

This year’s DVCon U.S. saw many great papers, posters, and tutorials; covering almost every aspect of functional verification. Thus, in…

SystemVerilog

The Semantics of SystemVerilog Syntax

Trying to grasp any programming language from scratch can be a difficult task, especially when you start by reading the…