As DVCon expands, we at Mentor Graphics have grown our sponsored sessions as well. Would you expect less? In DVCon’s…
UVM 1.2 Release is Imminent As vice chair of DVCon 2014, I can share with you that the Universal Verification…
One of the nice things about DVCon is the update one can get from the developers of IEEE and Accellera…
IEEE 1801™-2013 Enters Pre-Publish Phase The completion and approval of electronic design automation standards has seemed to be the order…
IEEE Std. 1800™-2012 Officially Ratified The IEEE Standards Association (SA) Standards Board (SASB) officially approved the latest SystemVerilog revision, Draft…
Accellera Ushers in Unified Coverage Interoperability Standard (UCIS) For the past few months, Accellera’s Unified Coverage Interoperability Standards working group…
In his recent post on UVM: Some Thoughts Before DVCon, Dennis outlined some great ideas about what we think should…
It is time to talk about what happens next with UVM The Design and Verification Conference (DVCon) has become the…
Wally Rhines DVCon 2011 Keynote Highlights Survey on Verification Languages OK, maybe it is not the Dawning of the Age…
