In a recent post on deepchip.com John Cooley wrote about “Who Knew VIP?”. In addition, Mark Olen wrote about this…
A colleague recently asked me: Has anything changed? Do design teams tape-out nowadays without GLS (Gate-Level Simulation)? And if so,…
“Who Knew?” about verification IP (VIP), was the theme of a recent DeepChip post by John Cooley on December 18. …
My Feb. 4 post introduced Mentor Graphics’ three-step FPGA verification process intended to help design teams get out of the…
As DVCon expands, we at Mentor Graphics have grown our sponsored sessions as well. Would you expect less? In DVCon’s…
Marketing teams at FPGA vendors have been busy as the silicon nanometer geometry race escalates. Altera is “delivering the unimaginable”…
MENTOR GRAPHICS AT ARM TECHCON This week ARM® TechCon® 2013 is being held at the Santa Clara Convention Center from…
We are truly living in the age of SoC design, where 78 percent of all designs today contain one or…
Verification Techniques & Technologies Adoption Trends This blog is a continuation of a series of blogs that present the highlights…
