SystemVerilog

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Simulation is Key in design verification process

The importance of simulation in the pursuit of absolute speed!

April 2, 2024

A casual conversation with an ex-insider of the high frequency trading sector reveals surprising details about simulation and their design-verification process

By Sunil Sahoo
3 MIN READ
SystemVerilog

Get your free copy of the IEEE 1800-2023 SystemVerilog LRM

March 4, 2024

At last year’s Design & Verification Conference (DVCon), I presented a few changes to the upcoming revision to the SystemVerilog…

By Dave Rich
< 1 MIN READ

UVM Objections at DVCON US 2024 – and Grape Jelly

February 22, 2024

Boiling Grape Jelly Stay with me – trust me. There’s a tie in to UVM Objections and DVCON US 2024….

By Rich Edelman
3 MIN READ

Welcome to the enhanced Verification Academy 2.0 forums!

January 30, 2024

We’ve recently enhanced the Verification Academy, moving to an all new platform. The Verification Academy is the industry’s leading resource…

By Dave Rich
2 MIN READ

Welcome to Verification Academy 2.0!

January 15, 2024

Step into the enhanced Verification Academy 2.0! After a year of meticulous development, we are thrilled to unveil its array…

By Harry Foster
2 MIN READ

IEEE Honors Siemens Employees for Dedication to Standards Development

December 12, 2023

Annually, the IEEE Standards Association (IEEE SA) recognizes outstanding participation across a variety of technical areas of standards development, leadership,…

By Tom Fitzpatrick
2 MIN READ
UVM Debug? Just nature doing what it does

Bent Tools and other Horrors From the Garden and UVM Debug – or Are You Still Debugging with $display?

May 24, 2023

I can’t take credit for the great flowers in the garden. It’s the tremendous rain we’ve had in California this…

By Rich Edelman
4 MIN READ
Pool of parameterized handles in SystemVerilog

Groups of Class Specializations in SystemVerilog

April 25, 2023

Introduction In a previous post, I said that in SystemVerilog, once you specialize a class, you can not make a…

By Chris Spear
3 MIN READ
The UVM string-based Factory can print base and derived objects

The UVM Factory Revealed, Part 2

January 25, 2023

Introduction This is a follow up to last week’s high-level post on the UVM Factory. Now let’s get technical! Here…

By Chris Spear
3 MIN READ