Accellera Approves New Co-Emulation Standard

Accellera Approves New Co-Emulation Standard

Standard Co-Emulation Modeling Interface (SCE-MI) 2.1 Improves Verification Productivity The Accellera Interface Technical Subcommittee (ITC) completed version 2.1 of the…

SystemVerilog Coding Guidelines: Package import versus `include

SystemVerilog Coding Guidelines: Package import versus `include

Another frequently asked question: Should I import my classes from a package or `include them? To answer this properly, you…

UVM: Joint Statement Issued by Mentor, Cadence & Synopsys

UVM: Joint Statement Issued by Mentor, Cadence & Synopsys

DAC Attendees Invited to Accellera’s Breakfast sponsored by Mentor, Cadence & Synopsys The full statement can be read at EDA…

OVM 2.0 Register Package Released

OVM 2.0 Register Package Released

In January 2010 we released the OVM 1.0 Register Package.  It has now been updated to enhance capabilities and address…

The Final Signatures (the meeting during the meeting)

The Final Signatures (the meeting during the meeting)

Accellera and The SPIRIT Consortium Merger is Complete An open SystemVerilog requirements gathering meeting sponsored by the IEEE Design Automation…

UVM Adoption: Go Native-UVM or use OVM Compatibility Kit?

UVM Adoption: Go Native-UVM or use OVM Compatibility Kit?

I shared information in my last blog that Mentor’s OVM-EA starter kit could be downloaded and used by those who…

UVM-EA (Early Adopter) Starter Kit Available for Download

UVM-EA (Early Adopter) Starter Kit Available for Download

Companion UVM-EA OVM Compatibility Overlay Kit Available for Download Mentor Graphics has made available its UVM-EA starter kit to promote…

Accellera Adopts OVM 2.1.1 for its Universal Verification Methodology (UVM)

Accellera Adopts OVM 2.1.1 for its Universal Verification Methodology (UVM)

Requirements set for Accellera UVM-EA (Early Adopter) Release This was a productive week for Accellera. After months of discussions, the…