At a recent SystemVerilog requirements gathering meeting,I was quite amused to see “deprecating features” come out as one of the…
EDA & VLSI Standards Focus Meeting on 12 March 2010 As part of its continuing program to reach out to…
… To Advance Technology for Humanity It is a humbling honor to have been elected chair of the IEEE Standards…
The SystemVerilog IEEE 1800-2009 Language Reference Manual (LRM) was published a few months ago with an unprecedented 472 updates. That’s…
I’m excited. I’ve had the pleasure of knowing Cliff Cummings for many years, and I was honored a couple of…
I see that Synopsys has finally released VMM1.2. Congratulations, guys. There will be plenty of opportunity over the coming weeks…
Just in time for the holidays! 🙂 IEEE Std. 1800™-2009, aka SystemVerilog 2009, is ready for purchase and download from…
SystemVerilog proved to be a “royal flush” of a reason for 100’s of people to gather together. Leaving poker references…
Another installment of “Longwinded Answers to Frequent SystemVerilog Questions: $root versus $unit” Believe me – I tried to make this…
