Part 6: The 2014 Wilson Research Group Functional Verification Study

Part 6: The 2014 Wilson Research Group Functional Verification Study

FPGA Language and Library Trends This blog is a continuation of a series of blogs related to the 2014 Wilson…

UVM Debug. A contest using class based testbench debug…

UVM Debug. A contest using class based testbench debug…

Still having fun doing UVM and Class based debug? Maybe a debug contest will help. I had a contest with…

No to Know VIP

No to Know VIP

In a recent post on deepchip.com John Cooley wrote about “Who Knew VIP?”. In addition, Mark Olen wrote about this…

March 2015 Edition of Verification Horizons Available Online!

March 2015 Edition of Verification Horizons Available Online!

With a name like “Fitzpatrick,” you knew I’d be celebrating today, right? Well, there’s no better way to celebrate this…

Portable Stimulus: A Small Step in Standardization

Portable Stimulus: A Small Step in Standardization

Accellera Approves Creation of Portable Stimulus Working Group At DVCon 2014, Mentor Graphics proposed Accellera launch an exploratory exercise, called…

Who Knew VIP?

Who Knew VIP?

“Who Knew?” about verification IP (VIP), was the theme of a recent DeepChip post by John Cooley on December 18. …

Preparing for the Perfect Storm with New-School Verification Techniques

Preparing for the Perfect Storm with New-School Verification Techniques

Between 2006 and 2014, the average number of IPs integrated into an advanced SoC increased from about 30 to over…

DVCon India: A Smashing Hit!

DVCon India: A Smashing Hit!

DVCon India, held in September 2014 in Bangalore, built on the Indian SystemC User Group meeting events and added a…

Accellera Approves UVM 1.2

Accellera Approves UVM 1.2

Accellera has announced the completion of a multi-year effort to update its latest edition of the Universal Verification Methodology (UVM). …