{"id":751,"count":156,"description":"","link":"https:\/\/blogs.stage.sw.siemens.com\/verificationhorizons\/tag\/systemverilog\/","name":"SystemVerilog","slug":"systemverilog","taxonomy":"post_tag","meta":[],"_links":{"self":[{"href":"https:\/\/blogs.stage.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/tags\/751","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.stage.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/tags"}],"about":[{"href":"https:\/\/blogs.stage.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/taxonomies\/post_tag"}],"wp:post_type":[{"href":"https:\/\/blogs.stage.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts?tags=751"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}